Thermal interfaces in microelectronics packages are commonly credited with a majority of the resistance for heat to escape from the chip to an attached cooling device (e.g. heat sinks, spreaders and the like). Thus, in order to minimize the thermal resistance between the heat source and cooling device, a thermally conductive paste, thermal grease or adhesive is commonly used. Thermal interfaces are typically formed by pressing the heat sink or chip cap onto the backside of the processor chip with a particle filled viscous medium between, which is forced to flow into cavities or non-uniformities between the surfaces.
It has been determined that stacking layers of electronic circuitry (i.e. 3 dimensional chip stack) and vertically interconnecting the layers provides a significant increase in circuit density per unit area. However, one significant problem of the three dimensional chip stack is the thermal density of the stack. For a four layer 3 dimensional chip stack, the surface area presented to the heat sink by the chip stack has only ¼ of the surface area presented by the two-dimensional approach. For a 4-layer chip stack, there are three layer-layer thermal interfaces in addition to the final layer to grease/heat sink interface. The heat from the bottom layers must be conducted up thru the higher layers to get to the grease/heat sink interface
On the chip side (i.e. the heat source), there usually exists hotspots, areas of higher power density, where most of the processing takes place, which results in a temperature gradient across the chip. These areas of higher heat and power density need to be kept within a set temperature range in order for the chip to perform properly and to pass quality and specification tests at the end of manufacturing.
Control of temperature distribution has been addressed by changing chip design/architecture. However, this requires expensive redesign of the microprocessor that may influence other operating parameters and does not address the present issues facing current high performance microprocessors.
Accordingly, it would be desirable to provide for reduced thermal resistance between heat sources and a cooling device that is both efficacious and yet not require changes to the microprocessor fabrication process.